tc358766 display bridge for displayport? connectivit y int d2dp description the toshiba tc358766 display bridge is optimized for handheld devices using a host processor with mobile industry processor interface (mipi) display serial interface (dsi) or display pixel interface (dpi) connectivity. the tc358766 functions as a protocol bridge enabling the video stream from the host processor dsi link or dpi link to drive a single or two independent displayport panel(s). the tc358766 has a dsi receiver that can be configured to support up to four dsi lanes with data rates up to 1 gbps per lane, for maximum total bandwidth of 4 gbps. it also has a dpi receiver that can be configured to support 16, 18 or 24 bits parallel interfaces and can be operated up to 154 mhz parallel clock. the displayport transmitter can be configured to support a single main link with one or 2 lanes or dual main links with single lane per link. the data throughput is 1.62 gbps or 2.7 gbps per lane of the displayport main link. as the displayport interface uses fewer lines and power consumption is more efficient, availability and usage of highresolution displayport panels is becoming a feature in handheld applications such as tablets and netbooks. the toshiba tc358766 display bridge can support displays with resolution up to 1920 x 1200 (wuxga) at 24 bits per pixel, at refresh rate of 60 frames per second. the tc358766 can support both an embedded displayport panel (edp) or an external dp panel at one time or simultaneously. the tc358766 bridge supports audio streaming from the application processor through the i 2 s interface. the audio is transmitted through the displayport link if the application requires, i.e. connecting to an external panel. the tc358766 is a 120-pin device, in a small package size of 6 mm x 6 mm, 0.50 mm ball pitch designed for portable products. highlights ? display bridge for connectivity of displayport tm panels to the application processors with a mobile industry processor interface (mipi) display serial inte rface (dsi) or display pixel interface (dpi). ? solutions based on the latest versions of the industry standard mipi dsi 1.01 to ensure high speed data rates of up to 1 gbps per lane and mipi dpi 2.0 to ensure speed of 154 mhz. ? display port transmitter features vesa displayport 1.1a standard that supports 1. 62 or 2.7 gbps per lane; and configurable to single or dual lane per main link. ? supports high-resolution displayport panels up to wuxga 1920 x 1200 at refresh rates of 60 fps. ? applicable to products such as t ablets, ebooks, netbooks and laptops. product brie f tc358766xbg system block diagram hpd1 refclk hpd0 dpln0 dpln1 aux_chd a ux _ ch1 v/hsync,de pclk spi_ss spi_clk/scl spi_mosi/sda spi_miso test rstx i 2 s data 24 i 2 s i/f dpi tx dpi rx baseband application processor dsi tx data buffer data lane 0 regfile displayport data lane 1 1.62/2.7 gbps two data lanes cg spi/i 2 c slave data lane 2 data lane 3 dsi rx video packet video p acket c video packet video packet video packet video packet c clk lane
features dsi receiver ? mipi dsi: v1.01 / mipi d-phy: v1.0 compliant. ? up to four (4) data lanes with bi-directional support on data lane 0. ? maximum speed at 1 gbps/lane. ? video input data formats: ? rgb-565, rgb-666 and rgb-888. ? new dsi v1.02 data type support: 16-bit ycbcr 422 ? interlaced video mode is not supported. dpi receiver ? maximum speed at 154 mhz. ? video input data formats: rgb-565, rgb-666 and rgb-888. i 2 s audio interface ? supports sampling frequencies of 32, 44.1, 48, 88.2, 96, 176.4 & 192 khz. ? supports up to 2 audio channels. ? optionally inserts iec609 58 status bits and preamble bits per channel. displayport interface ? high-speed serial bridge chip using vesa displayport 1.1a standard. ? supports one dual-lane port for high bandwidth application or two single-lane ports for connection to two displayport panels. ? supports 1.62 or 2.7 gbps/lane data rate with voltage swings @0.4, 0.6, 0.8 or 1.2v ? support of pre-emphasis levels of 0, 3.5 db and 6 db. ? aux channel supported at 1 mbps. ? supports hdcp encryption version 1.3 amendment for displayport revision 1.1. ? sscg with ~30 khz modulation to reduce emi. i 2 c interface ? i 2 c slave interface for debugging and/or chip register set access. spi interface ? spi slave interface for chip register set access. ? spi interface support for up to 30 mhz operation. clock source ? displayport clock source can be derived from an external clock input or from the dsi clock. acceptable clock values from external source or dsi clock derivatives are 13, 26, 19.2 or 38.4 mhz. power supply inputs ? core and mipi d-phy: 1.2v ? digital i/o: 1.8v ? displayport phy and pll: 1.8v and 1.2v package ? tc358766xbg: 120-pin, 6.0 mm x 6.0 mm, 0.5 mm ball pitch, 1.0 mm height north america toshiba america electronic components inc irvine, ca san jose, ca tel: (949) 623-2900 tel: (408) 526-2400 product brie f tc358766 display bridge for displayport? connectivity sales offices europe toshiba electronics europe gmbh dsseldorf, germany puteaux cedex, france tel: (0211) 5296-0 tel: (1) 47282181 farnborough, hampshire , u.k. tel: (0870) 060-2370 asia toshiba electronics (shanghai) co.,ltd toshiba electronics asia ltd shanghai, china shenzhen, china hong kong tel: (021) 6139-3888 tel: (0755) 2399-6897 tel: 2375-6111 toshiba electronics asia(singapore) pte. ltd. toshiba electronics taiwan corp. tel: (6278) 5252 taipei city tel: (02) 2508-9988 : toshiba electronics korea corp. seoul tel: (02) 3484-4334
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